1. Field of the Invention
The present invention relates to a coreless packaging substrate and a method for manufacturing the same, and, more particularly, to a light weighted and compact coreless packaging substrate, and a method for manufacturing the same.
2. Description of Related Art
As the electronic industry develops rapidly, researches move towards electronic devices with multifunction and high efficiency. Hence, circuit boards with lots of active and passive components and circuit connections thereon transfer from single-layered boards to multiple-layered boards so that the requirements such as integration and miniaturization in semiconductor packaging substrate can be met. Furthermore, interlayer connection technique is also applied in this field to expand circuit layout space in a limited circuit board and to meet the demand of the application of high-density integrated circuits.
For manufacturing conventional semiconductor packaging structures, a chip is mounted on the top surface of a substrate first, and then connected thereto by wire bonding. Alternatively, the chip is connected with the substrate by flip chip technique. Subsequently, solder balls are disposed on the bottom surface of the substrate and electrically connected to a printed circuit board. However, even though the purpose of high quantity pin counts can be achieved through the method illustrated above, the electrical performance of a device operated in high frequency or at high speed can be unstable or limited due to the long paths of conductive circuits. Moreover, the complexity of the manufacturing process is relatively increased because many connective interfaces are required for conventional semiconductor packaging structures.
In the method for manufacturing a flip-chip substrate, a packaging substrate is formed by providing a core board at first, and then followed by drilling, metal electroplating, plugging, circuit patterning, and so on to complete an inner structure. Subsequently, a multilayer substrate is afforded by built-up processes, as shown in FIGS. 1A to 1E, which show a flowchart for manufacturing a built-up type multilayer substrate. In FIG. 1A, a core board 11 is prepared first. The core board 11 includes a core layer 111 having a predetermined thickness, and a circuit layer 112 formed thereon. Meanwhile, the core layer 111 has a plurality of plated through holes (PTHs) 113 formed therein so that the PTHs 113 can be electrically connected to the circuit layer 112 on the core layer 111. As shown in FIG. 1B, the core board 11 is processed through a built-up process. The built-up process is illustrated as follows. First, a dielectric layer 12 is disposed on the surface of the core board 11. The dielectric layer 12 has a plurality of vias exposing part of the circuit layer 112 serving as conductive pads 112a. With reference to FIG. 1C, a seed layer 14 is formed by electroless plating or sputtering on the surface of the dielectric layer 12. Then, a patterned resist layer 15 is formed on the seed layer 12 so that the conductive pads 112a can be exposed by a plurality of openings 150 formed in the resist layer 15. With regard to FIG. 1D, conductive vias 16a and a patterned circuit layer 16 are formed by electroplating respectively in the vias and in the openings 150 of the resist layer 15. The circuit layer 16 can be electrically connected to the conductive pads 112a by the connection of the conductive vias 16a. Subsequently, the resist layer 15 and the seed layer 14 covered thereby are removed to afford a first circuit built-up structure 10a. Referring to FIG. 1E, a second built-up structure 10b is formed on the surface of the first built-up structure 10a in the same manner as the first built-up structure 10a so that a multilayer packaging substrate 10 is obtained.
The above-mentioned manufacturing begins from provision of a core board, followed by drilling, metal electroplating, plugging, circuit patterning and so on to complete an inner structure, and finally to performing built-up processes to afford a multilayer packaging substrate. However, in the manufacturing illustrated above, there is a need to form PTHs by drilling and electroplating etc. Therefore, many circuit layout spaces are occupied by the PTHs because the diameter and the depth of each PTH are greater than those of each conductive via. Moreover, undesirable cross-talk, noises, or signal decay resulting from excessive length of signal transmitting pathway could easily occur. In order to solve the disadvantages arising from long signal transduction pathway, the design of the circuit layout is often dense on a chip disposition side electrically connected to a chip. In contrast, the density of the circuit layout on a solder ball disposition side connected to a printed circuit board could be sparse. For most of the packaging substrates, the numbers of the circuit layers on the both sides are identical. When the density of the circuit layout on the solder ball disposition side is too sparse, not only many layout spaces are idle, but also the number of laminated layers is increased. Because multiple circuit layers need to be included, manufacturing processes become more complex. In addition, the packaging substrate is hard to be used in high frequency because of long conductive circuits and high impedance.